PURPOSE: To minimize the peak of a current to charge and discharge a load capacity and to prevent a malfunction by connecting the gate electrode of a third P channel and an N channel type MOS transistor to other edge of a delaying circuit.

CONSTITUTION: A P channel type MOS transistor QP 1 is connected between an output terminal N5 and a VDD, an N channel type MOS transistor QN 1 is connected between the output terminal N5 and a GND, and P channel type MOS transistors QP 2 and QP 3 are serially connected through a common connecting point N3 between the output terminal N5 and the VDD. N channel type MOS transistors QN 2 and QN 3 are serially connected through a common connecting point N4 between the output terminal N5 and the GND, QP 1 and 2 and QN 1 and 2, which are respective gate electrodes, are all connected to an input terminal 11, the gate electrode of QP 3 and QN 3 is connected to a nodal point N2 and to the N2, the output of a delaying circuit 1 with the N1 as an input is connected. Thus, the peak value of the VDD and GND currents at the time of being an output buffer action can be lowered.