Title:
OUTPUT BUFFER CIRCUIT
Document Type and Number:
Japanese Patent JPH0697433
Kind Code:
A
Abstract:
PURPOSE: To prevent the reverse flow of a current from the output terminal of an output buffer circuit to a power source, and suppress the level drop of an output signal, and improve the rise speed of the output signal and trailing speed.
CONSTITUTION: A nondoped n-channel MOS transistor Tr9 is connected between transistors Tr8 and Tr10, and the gate of the transistor Tr9 is connected to Vcc. Moreover, a nondoped n-channel MOS transistor Tr11 and an n-channel MOS transistor Tr12 are connected in series between Vcc and GND, and an output signal OUT is outputted from the output terminal To connected to the source of the transistor Tr11, and the threshold of the transistor Tr11 is set to 0V or over.
Inventors:
OGURA KIYONORI
Application Number:
JP24227692A
Publication Date:
April 08, 1994
Filing Date:
September 10, 1992
Export Citation:
Assignee:
FUJITSU LTD
FUJITSU VLSI LTD
FUJITSU VLSI LTD
International Classes:
H01L29/78; H03K5/02; H03K19/0175; (IPC1-7): H01L29/784; H03K5/02; H03K19/0175
Attorney, Agent or Firm:
Hironobu Onda
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