Title:
OUTPUT BUFFER CIRCUIT
Document Type and Number:
Japanese Patent JPS6462016
Kind Code:
A
Abstract:
PURPOSE: To provide an output buffer from a complementary metal-oxide- semiconductor(CMOS) to an emitter coupled logic(ECL) while having satisfactory performance concerning the fluctuation of an ECL output voltage by preventing an output current from a current source from depending on a power supply voltage and preventing an output voltage from the buffer from depending on the power supply voltage as well. CONSTITUTION: This circuit is provided with a current source 17 connected to a 1st power source Vss, 1st transistor 16 of 1st conductivity type for selectively connecting the current source to an intermediate node corresponding to the logic input signal of CMOS, 1st resistor having a prescribed resistance value R18 and connected between a 2nd power source Vcc and the intermediate node, and bipolar transistor 19 having a base, collector and emitter to respectively connect the collector to the 2nd power source, the base to the intermediate node and the emitter to the output node. Further, a 2nd conductive type of a 2nd transistor 14 is provided for selectively connecting the intermediate node to the 2nd power source corresponding to the logic input signal of CMOS. Thus, an improved output buffer 10 from CMOS to ECL can be provided.
Inventors:
BAANAADO RII MORISU
Application Number:
JP20749688A
Publication Date:
March 08, 1989
Filing Date:
August 23, 1988
Export Citation:
Assignee:
AMERICAN TELEPHONE & TELEGRAPH
International Classes:
H03K19/00; H03K19/013; H03K19/0175; H03K19/08; H03K19/0944; H03K19/0948; (IPC1-7): H03K19/00
Domestic Patent References:
| JPS5967728A | 1984-04-17 |
Attorney, Agent or Firm:
Hirofumi Mimata