PURPOSE: To minimize the time change of a current flowing in a power line and to reduce switching noise by sequentially driving plural output transistors different in current driving capacity with delaying a time and driving the transistors later as the current driving capacity is larger.

CONSTITUTION: The current driving capacity of the output transistors 20-2n on the side of a P channel are made small in the order of 20, 21,..., and that of the output transistors on the side of an N channel in the order of 30, 3n,... resistances 40-4n are respectively inserted between the output terminal of a prebuffer 1 and the gates of the transistors 20-2n, and the resistances 50-5n are respectively inserted between the output terminal of the prebuffer 1 and the gates of the transistors 30-3n. The values of the resistances 40-4n are made larger in the order of 4n,..., 41 and 40, and those of the resistances 50-50 in the order of 5n,...51 and 50. Respective resistances 4 and 5 constitute a signal delay circuit by a CR time constant with respective gate input capacitors which parasitically exist in the gates of the transistors 2 and 3 to which either ends of respective resistances 4 and 5 are connected.