Title:
OUTPUT CIRCUIT
Document Type and Number:
Japanese Patent JP3516569
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent delay time from being extremely extended when an output load is increased by providing the control signal of control circuit from 3rd and 4th transistors connecting their respective control electrodes with the control electrodes of 1st and 2nd transistors while being parallelly connected with the serially connected 1st and 2nd transistors for driving the output load.
SOLUTION: A circuit A is provided while being composed of PMOS 105 and NMOS 106, which are operated similarly to PMOS 107 and NMOS 108 for driving the output load, and an output SOUT of circuit A is connected to a control circuit B. The ON/OFF of PMOS 102 and NMOS 103 inside the control circuit B is performed by SOUT. Thus, a transient current to pass through PMOS 107 and NMOS 108 for driving the output load in case of change from ON to OFF can be suppressed and controlled in spite of the output load even when the output load is increased so that acceleration in the case of output load increase can be attained.
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Inventors:
Kono, Harumi
Application Number:
JP9572497A
Publication Date:
April 05, 2004
Filing Date:
April 14, 1997
Export Citation:
Assignee:
OKI MICRO DESIGN MIYAZAKI:KK
OKI ELECTRIC IND CO LTD
OKI ELECTRIC IND CO LTD
International Classes:
H03K17/04; H03K17/16; H03K17/687; H03K19/01; H03K19/0175; (IPC1-7): H03K19/0175; H03K17/04; H03K17/16; H03K17/687; H03K19/01
Attorney, Agent or Firm:
大西 健治
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