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Patent Searching and Data


Title:
OUTPUT CIRCUIT
Document Type and Number:
Japanese Patent JPH04172012
Kind Code:
A
Abstract:

PURPOSE: To reduce the noise of a power source by sensing that an output level is turned into an intermediate potential, and operating a current supply from the intermediate potential by an output transistor whose driving ability is high.

CONSTITUTION: The input of a first inverter 1 is connected with an input terminal, the output is connected with the input of a first prebuffer 2, and the output of the first prebuffer 2 is connected with the input of a first output buffer 15. And also, the output of the first inverter 1 is inputted to the gates of first and second selected-circuits 21 and 22, and the output of the first selected-circuit 21 is connected with the input of a second inverter 16, and the output of the second selected-circuit 22 is connected with a third inverter 17. Moreover, the output of a second output buffer 23 which is constituted by connecting the output of the second inverter 16 with the input of a cascade-connected P channel transistor 13, and connecting the output of the third inverter 17 with the input of an N channel transistor 14, is connected with an output terminal. Thus, an output circuit in which a power inducing noise is reduced can be obtained.


Inventors:
HATAKEYAMA SHIGERU
Application Number:
JP30010790A
Publication Date:
June 19, 1992
Filing Date:
November 06, 1990
Export Citation:
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Assignee:
NIPPON ELECTRIC IC MICROCOMPUT
International Classes:
H03K17/16; H03K17/687; H03K19/0175; H03K19/0185; (IPC1-7): H03K17/16; H03K17/687; H03K19/0175; H03K19/0185
Attorney, Agent or Firm:
Uchihara Shin