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Title:
OUTPUT CIRCUIT
Document Type and Number:
Japanese Patent JPH0522110
Kind Code:
A
Abstract:

PURPOSE: To obtain the output circuit which can reduce energy consumption.

CONSTITUTION: When an enable signal EN is at a low level, both a Pch transistor 8 and an Nch transistor 9 are turned off. At such a time, a Pch transistor 7 is turned on because an output signal (a) of a NAND gate 6 is at a low level. Thus, an output terminal is pulled up through the Pch transistor 7. On the other hand, when the enable signal EN is at a high level, an output signal OUT having the same phase as an input signal IN is outputted to the output terminal. At such a time, the Pch transistor 7 is turned off because the output signal (a) of the NAND gate 6 is at the high level. Therefore, a through current can be prevented from flowing between a power source VDD and a ground GND, and the energy consumption can be reduced.


Inventors:
YAMAGUCHI HISASHI
Application Number:
JP19864891A
Publication Date:
January 29, 1993
Filing Date:
July 12, 1991
Export Citation:
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Assignee:
NIPPON ELECTRIC IC MICROCOMPUT
International Classes:
H03K17/16; H03K19/0175; (IPC1-7): H03K17/16; H03K19/0175
Attorney, Agent or Firm:
Masanori Fujimaki



 
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