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Patent Searching and Data


Title:
OUTPUT CIRCUIT
Document Type and Number:
Japanese Patent JPS56140726
Kind Code:
A
Abstract:

PURPOSE: To enable to form a system that includes various kinds of integrated circuits such as TTL, CMOS and single-channel MOS by using a depression-type MOS element for one side of a single-channel MOS type output circuit.

CONSTITUTION: When the input Vin is at one level, the enhancement-type MOS transistor T6 of N channel type is turned on. At the same time, the depression-type MOS transistor T5 of N channel type is turned on faintly since the signal obtained by inverting the input Vin via an inverter 15 is supplied to the gate of the transistor T5. Thus the O-level value is obtained at the output Vout. On the other hand, the transistor T6 is turned off when the input Vin is at zero level. At the same time, the gate voltage of the transistor T5 is 1 and accordingly the transistor T5 is turned on strongly. As a result, the value up to the power supply voltage VDD can be fully obtained for the output Vout.


Inventors:
MIYAZAWA KANICHI
AOKI KAZUHIDE
SHINDOU SHIYOUJI
MAEDA HIROYUKI
Application Number:
JP4301280A
Publication Date:
November 04, 1981
Filing Date:
April 02, 1980
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H03K19/0185; H03K19/0944; (IPC1-7): H03K19/00
Domestic Patent References:
JPS5056142A1975-05-16
JPS53102660A1978-09-07