PURPOSE: To obtain a logic circuit with less noise disturbance onto an analog circuit by providing a means not giving a through-current to a P-channel MOS transistor (TR) of an output driver and an N-channel MOS TR to a pre-stage of the output driver circuit and suppressing the peak current of charging/ discharging from the load capacitance.

CONSTITUTION: When a level of an input terminal I changes from '1' to '0', the output of a NAND 3 changes from '0' to '1' and a P-channel MOS TR Pch1 changes from ON to OFF. Similarly, the P-channel TR Pch2 changes from ON to OFF after a prescribed time through delay inverters 5, 6 and a P-channel MOS TR Pch3 changes from ON to OFF after a prescribed time through delay inverters 7, 8. Then the output of the delay inverter 4 changes from '1' to '0' and the output of the NOR 1 changes from '0' to '1'. The N-channel TR Nch1 is turned on and a load capacitance CL is being discharged. Thus, the noise of the peak current due to the charge/discharge from the load capacitance is prevented.