Title:
OUTPUT DRIVING CIRCUIT AND CONTROL OF PULL-UP DRIVING TRANSISTOR
Document Type and Number:
Japanese Patent JPH08251001
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To select an output high-level maximum voltage by controlling a reference current and a mirror current by a bias current source and selecting a bias voltage output for a source voltage. SOLUTION: An output buffer bias circuit 22 includes a voltage reference regulator 24 which outputs an adjustment voltage VOHREF. The circuit 22 includes a bias current source 26 which is controlled with the clock signal generated on a line C50 by a timing control circuit 14. This current source 26 generates a bias current iBi As to be used by the regulator 24 when a voltage is generated on a line VOHREF. Then the regulator 24 receives an offset compensation current iNULL from an offset compensation current source 28. Further, the circuit 22 includes a V1 shift circuit 30 which is useful to set a voltage VOREF and supplies the set voltage VOHREF to an output buffer 21. Then the circuit 22 controls all buffer circuits 21 fully and receive the complementary data input generated by a readout circuit 19.
Inventors:
DEIBUITSUDO SHII MATSUKURUA
Application Number:
JP33228695A
Publication Date:
September 27, 1996
Filing Date:
December 20, 1995
Export Citation:
Assignee:
SGS THOMSON MICROELECTRONICS
International Classes:
H03K19/0175; G05F1/46; G11C11/407; H03K19/0185; H03K19/0948; (IPC1-7): H03K19/0175; H03K19/0948
Attorney, Agent or Firm:
Soga Doteru (6 people outside)
Previous Patent: BUS DRIVER AND BUS TRANSMISSION SYSTEM
Next Patent: HYBRID DATA PROCESSING SYSTEM HAVING BUILT-IN PULS POWER SUPPLY CMOS CIRCUIT
Next Patent: HYBRID DATA PROCESSING SYSTEM HAVING BUILT-IN PULS POWER SUPPLY CMOS CIRCUIT