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Title:
OUTPUT LEAKAGE REMOVING CIRCUIT FOR ANALOG SWITCHING CIRCUIT
Document Type and Number:
Japanese Patent JPH0262112
Kind Code:
A
Abstract:

PURPOSE: To completely eliminate the leakage current of an output transistor even when any load is connected by simultaneously making the output transistor into an off condition when an analog switching circuit goes to the non-conducting condition.

CONSTITUTION: By newly adding to an ordinary analog switching circuit, a second switching circuit 8 is provided. The circuit 8 is connected from a switching circuit input terminal 5 through a resistance R6 to the base of a NPN transistor T9 of an emitter being grounded from a switching circuit input terminal 5 through a resistance R6, and the collector is connected to the base connecting point of a PNP transistor T4 and a NPN transistor T5. Further, the collector of the transistor T4 is connected through a diode D1 to the collector of a NPN transistor T2. By such constitution, when a high potential is inputted to the input terminal 5 in order to make the analog switching circuit into the non-conducting condition, the circuit 8 becomes the on condition, simultaneously when a current source 3 is interrupted, the transistor T9 is on, the base potential of the transistor T5 goes to the ground potential, and the transistor T5 turned completely off.


Inventors:
YAMADA KOICHI
GOTO YASUHIRO
NAGAOKA JUNJI
Application Number:
JP21396788A
Publication Date:
March 02, 1990
Filing Date:
August 29, 1988
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03K17/06; H03K17/60; (IPC1-7): H03K17/06; H03K17/60
Domestic Patent References:
JPS61114614A1986-06-02
Attorney, Agent or Firm:
Akira Kobiji (2 outside)



 
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