Title:
OUTPUT POWER CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JPS6027918
Kind Code:
A
Abstract:
PURPOSE:To perform wide-range output control with constant efficiency by connecting plural diodes to the gate side of an FET amplifier, and supplying respective gate bias voltages in normal transmission, output electric power reduction, and output electric power disconnection from the cathodes of the diodes. CONSTITUTION:A gate-source voltage VGS is applied to a gate voltage terminal 17 all the time, a reference voltage is applied to a reference voltage terminal 13, and output electric power obtained at an output terminal 2 is held at, for example, 1W. When a control signal indicating when the output electric power is reduced is inputted to a control input terminal 3, a control circuit 20 is applied with the reference voltage and a specific voltage by associating the terminal 13 with a gate terminal voltage terminal 18, the FET amplifier 4 performs class ''C'' amplification, and the output at the terminal 2 is held at a specific value to reduce the current consumption. When a control signal indicating when the output electric power is cut off is inputted to the terminal 3, a voltage is applied from the circuit 20 to a gate voltage terminal 19, and the amplifier enters a cut-off state, so that no electric power is consumed. The diodes 14-16 operate as AND gates and the gate voltage of the amplifier 4 is determined by the voltage having the lowest level among voltages at the terminals 17-19.
Inventors:
ASAZAWA HIROSHI
Application Number:
JP13612183A
Publication Date:
February 13, 1985
Filing Date:
July 26, 1983
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
G05F1/56; (IPC1-7): G05F1/56
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)