Title:
出力レギュレータ
Document Type and Number:
Japanese Patent JP4271656
Kind Code:
B2
Abstract:
A duty cycle estimator comprises an error generator that compares an output of a switching regulator to a reference to generate an output error, wherein the switching regulator operates in accordance with a switching period. An accumulator determines an accumulated error of the output error over a time period of at least N times the switching period of the switching regulator, where N is an integer. An adjustment determiner adjusts a duty cycle for the switching regulator based on the accumulated error of the output error over the time period.
Inventors:
Starja Sahat
He Lansheng
Chan Cheongcheon
He Lansheng
Chan Cheongcheon
Application Number:
JP2004520097A
Publication Date:
June 03, 2009
Filing Date:
July 10, 2003
Export Citation:
Assignee:
Marvel World Trade Limited
International Classes:
H02M3/155; G05F1/40; G05F1/56; G05F1/575; H02M1/088; H02M3/137; H02M3/158; H02M3/335
Domestic Patent References:
| JP9140126A | ||||
| JP9149637A | ||||
| JP5049252A | ||||
| JP2001057778A | ||||
| JP2006042597A | ||||
| JP11146301A | ||||
| JP11187646A | ||||
| JP11289574A |
Foreign References:
| WO1997050165A1 |
Attorney, Agent or Firm:
Akihiro Ryuka