PURPOSE: To control a comparison reference voltage by sampling the output waveform from a signal output circuit having a differential pair constitution by plural clocks different by phases and using the average value of sampled data.

CONSTITUTION: This control circuit consists of a delay circuit which generates plural clock signals having the same speed and prescribed phase relations to an input signal, temporary storage circuits 2 and 3 which are triggered by plural clock signals from the delay circuit to temporarily store the output signal from the signal output circuit and correspond to plural clock signals respectively, average value circuits 4 and 5 which obtain the average values of outputs from plural temporary storage circuits 2 and 3 respectively, and a discriminating circuit 6 detects the difference between average value outputs from average value circuits 4 and 5 and controls the reference voltage given to the signal output circuit so as to minimize this difference.