Title:
オーバーレイ計測システム及びオーバーレイ計測装置
Document Type and Number:
Japanese Patent JP7254940
Kind Code:
B2
Abstract:
The present invention enables an overlay error between processors to be measured from a pattern image, the SN ratio of which is low. To this end, the present invention forms a secondary electron image 200 from a detection signal of a secondary electron detector 107, forms a reflected electron image 210 from a detection signal of a reflected electron detector 109, creates a SUMLINE profile 701 that is obtained by adding luminance information in the reflected electron image along the longitudinal direction of a line pattern, and calculates an overlay error of a sample by using position information about an upper layer pattern detected from the secondary electron image and position information about a lower layer pattern that is detected by using an estimation line pattern 801 estimated on the basis of the SUMLINE profile from the reflected electron image.
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Inventors:
Masataka Sugie
Sakai total
Sakai total
Application Number:
JP2021541781A
Publication Date:
April 10, 2023
Filing Date:
August 23, 2019
Export Citation:
Assignee:
Hitachi High-Tech Co., Ltd.
International Classes:
G01B15/00; G01N23/2206; G01N23/2251; H01J37/22; H01J37/28; H01L21/66
Domestic Patent References:
| JP201486393A |
Foreign References:
| WO2014181577A1 | ||||
| US7080330 |
Attorney, Agent or Firm:
Polar Patent Attorney Corporation
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