Title:
Overlay measuring device
Document Type and Number:
Japanese Patent JP6147879
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a method for easily and robustly measuring an overlay in an area where an actual device circuit pattern is formed in manufacturing a semiconductor device.SOLUTION: An overlay measuring method is a method for measuring an overlay of a semiconductor device in which a circuit pattern is formed through a plurality of times of an exposure step. The method includes: an image pickup step S601 of picking up images of a plurality of areas of the semiconductor device; a reference image setting step S603 of setting a reference image from among the plurality of picked-up images which are picked up in the image pickup step; a difference quantification step S604 of quantifying difference between the reference image set in the reference image setting step and the plurality of picked-up images which are picked up in the image pickup step; and an overlay calculation step S605 of calculating the overlay on the basis of the difference quantified in the difference quantification step.SELECTED DRAWING: Figure 6
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Inventors:
Minoru Harada
Ryo Nakagaki
Fumihiko Fukunaga
Yuji Takagi
Ryo Nakagaki
Fumihiko Fukunaga
Yuji Takagi
Application Number:
JP2016016835A
Publication Date:
June 14, 2017
Filing Date:
February 01, 2016
Export Citation:
Assignee:
Hitachi High-Technologies Corporation
International Classes:
G01B15/00; H01J37/22; H01L21/66
Domestic Patent References:
JP2011119471A | ||||
JP2006351888A | ||||
JP2008058166A | ||||
JP2011165479A |
Foreign References:
US7181057 |
Attorney, Agent or Firm:
Yuji Toda
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