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Title:
OVERLOAD PROTECTING CIRCUIT OF POWER SUPPLY UNIT
Document Type and Number:
Japanese Patent JPS60108921
Kind Code:
A
Abstract:
PURPOSE:To make a power supply unit escape from transient overload status generated at the rise of the power supply unit by actuating a protecting function with time delay at the detection of the 1st level or instantaneously at the detection of the 2nd level. CONSTITUTION:If the value of output current IOUT exceeds the 1st level I1 temporally at the rise of power supply, the output of the 1st operational amplifier U1 is increased. The output of the 2nd operational amplifier U2 does not exceed V1 until the output current IOUT reaches the 2nd level I2. The output signal of the operational amplifier U1 is delayed by a fixed time td by a delay circuit consisting of a resistor R1 and a capacitor C1. If the IOUT is reduced less than I1 during the period, the cathodos of diodes D1, D2 do not reach V1. Therefore, overload status is not generated. When the time during which the output current IOUT exceeds the 1st level I1 continues the delay time td or more, the cathodos of the D1, D2 are increased up to V1 and reach the overload level. Thus, the phenomenon interrupting the escape from the overload status at the rise of power supply can be interrupted.

Inventors:
SUGAWARA AKIHIRO
Application Number:
JP21717383A
Publication Date:
June 14, 1985
Filing Date:
November 18, 1983
Export Citation:
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Assignee:
YOKOGAWA HOKUSHIN ELECTRIC
International Classes:
G05F1/10; G05F1/573; H02H3/093; (IPC1-7): G05F1/573
Domestic Patent References:
JPS4941836A1974-04-19
JP58070091B
JPS5495881A1979-07-28
JP49075032B
JPS5144244A1976-04-15
Attorney, Agent or Firm:
Shinsuke Ozawa



 
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