Title:
非平衡型4相相関器を用いたPLL
Document Type and Number:
Japanese Patent JP2006505985
Kind Code:
A
Abstract:
A Phase Locked Loop (1) used in a data and clock recovery comprising a frequency detector (10) including a quadricorrelator (2), the quadricorrelator (2) comprising a frequency detector including double edge clocked bi-stable circuits (21, 22, 23, 24) coupled to a first multiplexer (31) and to a second multiplexer (32) being controlled by a signal having a same bitrate as the incoming signal (D), and a phase detector (DFF) controlled by a first signal pair (PQ, PQ provided by the first multiplexer (31) and by a second signal pair (PI, PI) provided by the second multiplexer (32).
Inventors:
Mihai, A.T.Sandureanu
Application Number:
JP2004549408A
Publication Date:
February 16, 2006
Filing Date:
October 08, 2003
Export Citation:
Assignee:
Koninklijke Philips Electronics N.V.
International Classes:
H03L7/113; H03D13/00; H03L7/085; H03L7/087; H03L7/091; H04L7/027
Domestic Patent References:
| JPH06216766A | 1994-08-05 | |||
| JP2000124801A | 2000-04-28 | |||
| JPH11308097A | 1999-11-05 |
Foreign References:
| US5757857A | 1998-05-26 |
Attorney, Agent or Firm:
Kenji Yoshitake
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
Akaoka Akira
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
Akaoka Akira