Title:
【発明の名称】浮遊ゲート型不揮発性半導体記憶装置の製造方法
Document Type and Number:
Japanese Patent JP2701332
Kind Code:
B2
Abstract:
PURPOSE:To reduce the capacity between a floating gate electrode and diffused layers for microminiturizing the structure and enhancing the memory performance by a method wherein a tunnel injection region is provided in an insular region specified by encircling thick silicon oxide films on one diffused layer as well as the other partly thick silicon oxide film is formed on the other diffused layer while the floating gate electrode and a control gate electrode are formed. CONSTITUTION:An n type diffused layers 4 and 6 are formed on a region to be formed into a tunnel injection region 8 and simultaneously thick silicon oxide films 18a and 18b are formed respectively on these diffused layers 4 and 6. After removing needless silicon nitride films 21 and silicon oxide films 20 as well as forming a gate insulating film 5 using thermal oxidizing process, a thin silicon oxide film 8' in the tunnel injection region 8 is formed in self- alignment in an insular region using the thermal oxidizing process again; a floating gate 9 is formed as if covering both of the thin silicon oxide film 8' and the thick silicon oxide films 18a, 18b; and after coating the whole surface with an insulating film 11, a control gate electrode 10 is formed.
Inventors:
Hidetoshi Nakata
Application Number:
JP17061888A
Publication Date:
January 21, 1998
Filing Date:
July 08, 1988
Export Citation:
Assignee:
NEC
International Classes:
H01L21/8247; H01L27/10; H01L27/115; H01L29/78; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP61194877A | ||||
| JP58130571A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)