PURPOSE: To improve operation speed by sufficiently boosting the gate potential of a MOS transistor(TR) on an output stage even if a reset period is short.

CONSTITUTION: Since an input signal DOHN is turned to 'H' when a reset period is started after the lapse of an initial output period, a node Ng is turned to VCC-VT stepped down by one step from the threshold voltage VT of an NMOS TR 62 through the NMOS TR 62. When an NMOS TR 44 is turned on and a node Nd is turned from 'L' to 'H', the potential of the node Ng is bootstrapped by the gate capacity of an NMOS TR 61. Since the NMOS TR 61 has the larger mutual transmission conductance than that of an NMOS TR 46, a node Ne reaches a prescribed potential level following the rise of the node Nd. Thereby the boot-strap potential of the node Ne is increased by the gate potential of an NMOS TR 49, the rise of a node Nb is also accelerated and a the bootstrap potential of the node Nb is increased by a capacitor 51, as well.