PURPOSE: To reduce the operating frequency of a presettable counter and to produce a multiple pulse that includes a fraction of cycle of a clock pulse.

CONSTITUTION: A presettable counter 1 counts the clock pulses received from a data input terminal 14, and this count output is detected by a detecting circuit 2. An integrating circuit 3 outputs the integrated value and the carry of data. A programmable delay circuit 4 delays the clock pulse by a time equivalent to the integrated value and produces a pulse having the multiple frequency including a fraction against the clock pulse. A shift circuit 5 is connected to the counter 1 and repeats the shift operations based on the clock pulse for output of clock pulses. The counter 1 counts these clock pulses for reduction of frequency of the counter clock pulse. Then the circuit 5 receives a carry signal from the circuit 3 and discontinues its shift operation for a prescribed time.