Title:
PWM信号生成回路
Document Type and Number:
Japanese Patent JP4404270
Kind Code:
B2
Abstract:
After an output signal S4 is level-inverted, first and second shorting FETs 55, 56 as a level-inversion inhibiting circuit inhibit level-inversion so that the signal is maintained to the inverted state. Thereafter the inhibition of level-inversion is released, when the signal is subsequently level-inverted at a proper time according to a desired duty ratio of a PWM signal S1. Thus chattering can be prevented and thereby a PWM signal S1 of a stable duty ratio can be generated, even if the level of a reference signal S3 fluctuates due to a noise or the like during vehicle acceleration, for example.
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Inventors:
Masayuki Kato
Seiji Takahashi
Masahiko Koto
Isshiki Isshiki
Seiji Takahashi
Masahiko Koto
Isshiki Isshiki
Application Number:
JP2007513548A
Publication Date:
January 27, 2010
Filing Date:
October 17, 2006
Export Citation:
Assignee:
Auto Network Technologies, Ltd.
SUMITOMO WIRING SYSTEMS,LTD.
Sumitomo Electric Industries, Ltd.
SUMITOMO WIRING SYSTEMS,LTD.
Sumitomo Electric Industries, Ltd.
International Classes:
H03K7/08; H03K4/08
Domestic Patent References:
| JP1141077A | ||||
| JP1197989A | ||||
| JP5168164A |
Attorney, Agent or Firm:
Akatsuki Joint Patent Office