Title:
PACKAGE BOARD AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JP3158089
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a package board capable of adequately connecting conductor wirings on an upper and lower layers via electrode layers.
SOLUTION: The manufacturing method comprises the steps of forming an inner layer Cu pattern 34U composed of a ground layer 34G and land-pads 41 on the surface of a core board 30, coating and curing smoothing resin on the surface of this CU pattern 34U, and polishing the resin 40 to cauvae the Cu pattern 34U exposed. In the Cu pattern forming step, insulating buffer zones 43 around the land-pads 41 are all surrounded with the ground layer 34G so as to avoid dropping the land-pads 41 in a process of polishing the resin 40 and having the Cu pattern 34U exposed, thereby enabling proper connection of conductor wirings running over the pattern 34U on the upper and lower layer.
More Like This:
Inventors:
Motoo Asai
Yoji Mori
Yoji Mori
Application Number:
JP36194697A
Publication Date:
April 23, 2001
Filing Date:
December 10, 1997
Export Citation:
Assignee:
IBIDEN Co., Ltd.
International Classes:
H05K3/46; H01L23/12; (IPC1-7): H01L23/12; H05K3/46
Domestic Patent References:
| JP7106741A | ||||
| JP832240A | ||||
| JP11121933A | ||||
| JP9298364A | ||||
| JP8288658A | ||||
| JP722754A | ||||
| JP61220398A | ||||
| JP6316498U | ||||
| JP61100178U |
Other References:
【文献】国際公開99/21224(WO,A1)
Attorney, Agent or Firm:
Akito Tagashita (1 person outside)