Title:
PACKAGE FOR FET
Document Type and Number:
Japanese Patent JPS5892243
Kind Code:
A
Abstract:
PURPOSE: To improve the band characteristic by the reduction of the input reflection coefficient of a GaAs MESFET, by providing an inductance to a source.
CONSTITUTION: The GaAs MESFET chip 6 is mechanically connected to a conductive layer 2 for source electrode, and the source electrode 7, the second gate electrode 8, the first gate electrode 9 and drain electrode 10 are connected respectively to the conductive layer 2 for source electrode, conductive layer 3 for the second gate electrode, conductive layer 4 for the first gate electrode and conductive layer 5 for drain electrode by metallic fine wires 11. Further, a conductive layer 12 for inductance wherein the conductive layer for source electrode is extended is provided.
Inventors:
IRIE MICHIO
IKI SHIGEO
IKI SHIGEO
Application Number:
JP19117381A
Publication Date:
June 01, 1983
Filing Date:
November 27, 1981
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L29/80; H01L21/338; H01L23/12; H01L23/64; H01L29/812; H01P5/08; H03F3/60; (IPC1-7): H01L23/12; H01L29/80
Attorney, Agent or Firm:
Masuo Oiwa