Title:
PACKAGE FOR HOUSING SEMICONDUCTOR CHIP
Document Type and Number:
Japanese Patent JP3181013
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To obtain a package which prevents an electric short-circuit from being generated between adjacent external lead terminals when the external lead terminals are deformed.
SOLUTION: In a package for housing a semiconductor chip, one end of every external lead terminal 7 is fixed to a container 4 whose inside comprises a space used to house the semiconductor chip, and the other end of every external lead terminal 7 is made to protrude to the outside from the side face of the container 4 so as to be attached to, and mounted on, an electric insulating connection member 8. Then, a plurality of metal layers 9 to and on which the other end of every external lead terminal 7 is attached and mounted and whose width is substantially identical to the width of every external lead terminal 7 are formed additionally on the surface of the coupling member 8 by keeping a prescribed interval, and protrusions 9a are formed alternately on respective sides of the respective adjacent metal layers 9.
Inventors:
Shuichi Fukudome
Application Number:
JP19952695A
Publication Date:
July 03, 2001
Filing Date:
August 04, 1995
Export Citation:
Assignee:
Kyocera Corporation
International Classes:
H01L23/50; (IPC1-7): H01L23/50
Domestic Patent References:
| JP62128191A | ||||
| JP2118946U |