Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
PACKAGE FOR PGA TYPE SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS6437842
Kind Code:
A
Abstract:

PURPOSE: To increase pins while improving airtightness and reliability, and to enhance profitability by welding a lead frame to a ceramic substrate with a recessed section for receiving a semiconductor element by low melting-point glass.

CONSTITUTION: A package for a pin grid array (PGA) type semiconductor device having a small mounting area is formed by a ceramic substrate 10 having a recessed section 12 for receiving a semiconductor element and high airtightness. A lead frame 20 is welded to sections except the recessed section 12 in the surface, to which the recessed section 12 is shaped, by low melting- point glass 18, and an internal conductive section is formed without metallizing the substrate 10. According to the constitution, pins are increased while airtightness, reliability and profitability are improved.


Inventors:
MURAMATSU SHIGEJI
Application Number:
JP19399287A
Publication Date:
February 08, 1989
Filing Date:
August 03, 1987
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
SHINKO ELECTRIC IND CO
International Classes:
H01L23/08; H01L21/60; H01L23/12; H01L23/50; (IPC1-7): H01L21/60; H01L23/08; H01L23/12; H01L23/50
Domestic Patent References:
JPS5958851A1984-04-04
Attorney, Agent or Firm:
Takao Watanuki