Title:
PACKAGE FOR SEMICONDUCTOR CHIP AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPH05109801
Kind Code:
A
Abstract:
PURPOSE: To reduce a failure occurrence rate in a conductive path to the lead of a lead frame from the bonding pad of a semiconductor chip via a bonding wire. CONSTITUTION: A lead 14 is mounted to a semiconductor chip 12 where a pad 15 is formed via an insulation layer 11. The pad and the lead corresponding to each other are connected by a wire 16. A thin film 18 where a paint film 17 of a thermosetting resin adhesive is applied and formed is overlapped so that it covers the surface of the lead, the wire, and the semiconductor chip and it contacts the paint film of the adhesive. The thin film is pressed for allowing the paint film to flow between the leads and, at the same time, the wire is pressed for pressing each wire to the surface of the lead and the pad where the wire is connected and then the adhesive is heated and cured. An additional electrical contact part is formed due to the pressing of the wire to the lead or the pad and is maintained conductive when the connection part of the original wire is broken.
Inventors:
EICHI WAADO KONRU
GEERII HIYUU AIRISHIYU
FURANSHISU JIYOSEFU PAKURUSUKI
UIRIAMU JIYON SURATSUTERII
SUTEIIBUN JIYOOJI SUTAA
UIRIAMU KIYARORU WAADO
GEERII HIYUU AIRISHIYU
FURANSHISU JIYOSEFU PAKURUSUKI
UIRIAMU JIYON SURATSUTERII
SUTEIIBUN JIYOOJI SUTAA
UIRIAMU KIYARORU WAADO
Application Number:
JP8091692A
Publication Date:
April 30, 1993
Filing Date:
April 02, 1992
Export Citation:
Assignee:
IBM
International Classes:
H01L21/56; H01L21/60; H01L23/495; H01L25/065; H01L25/07; H01L25/18; (IPC1-7): H01L21/60
Attorney, Agent or Firm:
Koichi Tonmiya (3 outside)