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Patent Searching and Data


Title:
PACKAGING METHOD OF SEMICONDUCTOR CHIP
Document Type and Number:
Japanese Patent JP2009117434
Kind Code:
A
Abstract:

To prevent solder solution of a thick film conductor as much as possible while ensuring solder wettability in a packaging method of a semiconductor chip arranged to connect a semiconductor chip consisting of a silicon semiconductor onto the thick film conductor on a ceramic substrate by solder die bonding.

A dissolution prevention film 11a for preventing a thick film conductor 11 comprising an active metal from dissolving into molten solder 30, a sacrifice film 11b which dissolves into the molten solder 30 more easily than the dissolution prevention film 11a and dissolves into the molten solder 30 sacrificially, and a wettability enhancement layer 11c which exhibits excellent wettability to the solder 30 as compared with the thick film conductor 11 and ensures excellent wettability are laminated sequentially on the surface of the thick film conductor 11 from the surface side, and then mounting of a semiconductor chip 20 through the solder 30 and connection by the solder 30 are performed.


Inventors:
WATANABE TAKESHI
MIZUTANI KOJI
Application Number:
JP2007285733A
Publication Date:
May 28, 2009
Filing Date:
November 02, 2007
Export Citation:
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Assignee:
DENSO CORP
International Classes:
H01L21/52
Attorney, Agent or Firm:
Yoji Ito
Takahiro Miura
Fumihiro Mizuno