PURPOSE: To minimize delay in an exchange with respect to a relay packet and to obtain a packet exchange with less in-network delay as the entire packet exchange by providing a processor bus and a DMAC bus to the packet exchange exclusively respectively.

CONSTITUTION: An exclusive bus 1 and a DMAC exclusive bus 2 are connected to a buffer 3 receiving a packet from a line and the buffer 3 is used for a 2-port buffer. Moreover, a processor 4 accesses directly the buffer 3 via an exclusive bus 1 to decide the type and destination of the packet. Simultaneously, the DMAC 5 accesses the buffer 3 through the exclusive bus 2 and starts the transmission through the exclusive bus 2 in the DMA operation to the buffer memory 3a in the state of no decision as to whether a packet to be relayed or not in the DMA operation. Then the processing to the packet and the transfer to the transmission buffer are progressed simultaneously and the delay in the exchange with respect to the relay packet is minimized.