Title:
PACKET MEMORY CIRCUIT AND PACKET STORAGE DEVICE
Document Type and Number:
Japanese Patent JP2003283579
Kind Code:
A
Abstract:
To provide a packet memory circuit and a packet storage device in which a probability of a packet loss to be caused by overflow of a queue is low.
A write area updating means 85 detects a storage area 311 in which data for a prescribed amount are written, makes a write area holding means 83 which holds area information indicating such a storage area newly hold unused area information stored in an unused area storage means 86 and adds the storage area to a queue 4 corresponding to the write area holding means.
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Inventors:
SUGIURA MIKITO
AOYAMA TAKAHIRO
AOYAMA TAKAHIRO
Application Number:
JP2002086509A
Publication Date:
October 03, 2003
Filing Date:
March 26, 2002
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H04L13/08; (IPC1-7): H04L13/08
Attorney, Agent or Firm:
Nihei Masataka