PACKET SPEED CONVERTER

Title:

PACKET SPEED CONVERTER

Document Type and Number:

Japanese Patent JP3444247

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To provide a packet speed converter which reduces consumption of bus band resources that is caused by the slow transfer capability and can use a 1394 bus of higher efficiency.
SOLUTION: An asynchronous packet that is received from a 1394 bus B1 or B2 is stored temporarily in a RAM 13. Then the synchronous packet undergoes the header conversion, is converted into a transfer rate based on the setting of a switch 14-1 or 14-2 and transmitted to the other 1394 bus. Meanwhile, a steam packet that is received similarly as the synchronous bus is outputted to a link layer LSI 31 or 32 through an isochronous packet transfer path S3, undergoes header conversion according to the setting of a steam control register of each link layer LSI, is converted into a transfer rate, based on the setting of the switch 14-1 or 14-2 and then is transmitted to each bus.

Inventors:

Wataru Domon
Junichi Matsuda
Shuntaro Yamazaki

Application Number:

JP27756199A

Publication Date:

September 08, 2003

Filing Date:

September 29, 1999

Export Citation:

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