PURPOSE: To adopt the configuration suitable for high speed processing and to reduce the circuit scale.

CONSTITUTION: When plural packets are inputted through plural incoming lines 103, they are stored simultaneously in a storage area designated by an address information from a control circuit 102 in a buffer memory 101. The control circuit 102 receives outgoing line information representing to which outgoing line 105 each packet is to be outputted through information 107 and outputs the address information to the buffer memory 101 based on the outgoing line information and outputs the plural packets to the outgoing line 105 simultaneously. The buffer memory 101 consists of a multi-port memory and a peripheral circuit and a structure expanding a structure of a general 2-port memory is adopted for the multi-port memory.