PURPOSE: To improve the speed of the packet switching process of a packet switchboard by reducing the processing time by sending packets arrived from an input line in a branched state after identifying the lines to which each packet is to be sent while the packets are shifted in a shift register.

CONSTITUTION: A line interface section 101 executes a data link level process on frames arriving from a communication line 2 housed in the section 101 and extracts a packet P. Then the section 101 inputs the packet P one bit by one bit to the packet data register 21 of a packet switching section 102 through an input line 106. In the stage where the destination address contained in the packet header PH of the packet P shifted in a packet data register 21 arrives at a destination address monitoring section 21DA, a comparing section 232 compares the destination address DA with a branching address A and, when they coincide with each other, sends the packet P to an output line 108 after branching the packet P.