Title:
PACKET TYPE MEMORY LSI WITH BUILT-IN CO-PROCESSOR, PACKET TYPE MEMORY/CO-PROCESSOR BUS AND CONTROL METHOD THEREFOR
Document Type and Number:
Japanese Patent JP3189727
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To control a co-processor part incorporated in a chip from a bus mater while using a simple bus protocol and simple bus constitution equivalent to the bus protocol and bus constitution of a conventional packet type memory LSI and a packet type memory bus.
SOLUTION: To the memory part 11 and co-processor part 14 of a packet type DRAM 1 with a built-in co-processor, respectively intrinsic memory device ID and co-processor device ID are imparted. The DRAM 1 is connected through an external input/output terminal 5 to a packet type memory/co-processor bus 2 provided with a single bus mater. A request packet received from the bus 2 is decoded in a control part 12, and when the request packet specifies the device ID of the memory part 11 or the co-processor part 14, the memory part 11 or the co-processor part 14 is accessed. By access from the bus mater to the co-processor part 14, an arithmetic operation start request and an arithmetic result request, etc., are performed to the co-processor part 14.
Inventors:
Masato Motomura
Application Number:
JP9758797A
Publication Date:
July 16, 2001
Filing Date:
April 15, 1997
Export Citation:
Assignee:
NEC
International Classes:
G06F13/16; G06F12/00; G06F12/06; G06F13/42; G11C7/00; (IPC1-7): G06F13/16; G06F12/00; G06F12/06; G11C7/00
Domestic Patent References:
| JP1222459A | ||||
| JP58192154A | ||||
| JP6215160A | ||||
| JP1049428A | ||||
| JP8227394A | ||||
| JP10143489A | ||||
| JP3154919A | ||||
| JP6341934A | ||||
| JP5507374A |
Other References:
村上和彰、外２名，“メモリ−マルチプロセッサ一体型ＡＳＳＰ「ＰＰＲＡＭ」用標準通信インタフェース『ＰＰＲＡＭ−Ｌｉｎｋ Ｓｔａｎｄａｒｄ』Ｄｒａｆｔ０．０の概要”，情報処理学会研究報告，社団法人 情報処理学会，平成８年８月，第９６巻，第８０号（９６−ＡＲＣ−１１９），ｐ．１５５−１６０
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)