Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3178190
Kind Code:
B2
Abstract:
PURPOSE: To provide a semiconductor integrated circuit in which a partial logic circuit can be tested with no influence from other neighboring partial logic circuit and all routes of each partial logic circuit, through which the data passes under normal mode, can be tested for failure.
CONSTITUTION: The semiconductor integrated circuit comprises a first partial logic circuit 102, a selector 110 receiving the output from the first partial logic circuit 102, a second partial logic circuit 103 receiving the output from the selector 110, and a flip-flop 109 receiving the output from the selector 110. The flip-flop 109 is connected with a scan path and can control the output value while observing the input value through scanning operation. The selector 110 selects any one of the output from the first partial logic circuit 102 or the flip-flop 109 under external control and delivers the selected one.
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Inventors:
Sadami Takeoka
Akira Motohara
Akira Motohara
Application Number:
JP26076393A
Publication Date:
June 18, 2001
Filing Date:
October 19, 1993
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H01L21/66; G01R31/28; (IPC1-7): G01R31/28
Domestic Patent References:
| JP5281308A | ||||
| JP5322993A |
Attorney, Agent or Firm:
Fumio Iwahashi (2 others)