Title:
PAGE-IN BURST-OUT FIFO
Document Type and Number:
Japanese Patent JP2960342
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To shorten the transferring time at the time of transferring data to a DRAM using a high-speed page mode by collecting a plurality of words having the same row address to one storage device.
SOLUTION: An interface FIFO between a system bus and DRAM is designed to shorten data transfer waiting time by using the page mode cycle of the DRAM. When a SAMEPAGEN signal is issued, a status machine 20 operates and, when a WCNT signal exceeds an RCNT signal by a preset amount, issues a DRAMREQ signal. However, when the issuing of the SAMEPAGEN signal is stopped and it is indicated that a new different address exists on an ADRBVS 12, the machine 20 issues an FULLN signal. Then the machine 20 prevents the input of data until a PIBO 10 becomes empty and issues an FLUSHN signal so as to transfer all data stored in a data register to the DRAM. Thereafter, page-mode transfer is performed.
Inventors:
CHIA RUN HANGU
Application Number:
JP32255895A
Publication Date:
October 06, 1999
Filing Date:
November 02, 1995
Export Citation:
Assignee:
SAMUSUN SEMIKONDAKUTAA INC
International Classes:
G11C7/00; G06F5/06; G11C7/10; G11C8/04; G11C11/401; (IPC1-7): G11C7/00; G11C7/00
Domestic Patent References:
| JP5165714A | ||||
| JP478843U |
Attorney, Agent or Firm:
Akira Asamura (3 outside)