Title:
PARALELL COMPUTER SYSTEM
Document Type and Number:
Japanese Patent JP2538185
Kind Code:
B2
Abstract:
PURPOSE: To provide a processing chip used in a computer using an extremely large number of parallel processors in which plural processors and dynamic memories are included.
CONSTITUTION: Each processing chip 35 constituting an array is provided with a reading/writing memory and a processor which can output based on read data and instruction information. Stored data are transmitted to the relevant processors in parallel by a register identified based on an address received through plural registers provided at the parallel processing chips 35, and processing data received form the relevant processors are stored in the register identified by the address signal.
Inventors:
TABURYUU DANIERU HIRISU
Application Number:
JP28934993A
Publication Date:
September 25, 1996
Filing Date:
November 18, 1993
Export Citation:
Assignee:
DABURYUU DANIERU HIRISU
International Classes:
G06F15/16; G06F15/173; G06F15/80; G06T1/20; (IPC1-7): G06F15/16; G11C11/406
Domestic Patent References:
| JP55115155A | ||||
| JP57155659A | ||||
| JP5611683A |
Attorney, Agent or Firm:
Yoshikazu Tani (1 person outside)