PURPOSE: To increase a data communication speed and to perform a multistage pixel shifting processing such as the rearrangement of pixel data in a short time by providing a shift register which performs data shifting operation with an operation clock of frequency higher than the operation clock of plural processors and performing data transfer among the processors through the shift register.

CONSTITUTION: Pixel data outputted from the respective processors 26 are supplied to IPC registers 36, which are connected in a loop and placed in shifting operation with the clock nMCLK of frequency (n) times as high as the operation clock MCLK of the processors 26. Then while the pixel data are shifted in order in the IPC registers 36, specific pixel data are fetched by the processors 26, so the data communication speed among the respective processors 26 can be increased to nearly (n) times as fast as before, and the multistage pixel shifting processing such as the rearrangement of the pixel data can be performed in a time which is nearly 1/n time as short as usual.