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Title:
PARALLEL BRANCHING PROCESSOR
Document Type and Number:
Japanese Patent JPH07262008
Kind Code:
A
Abstract:

PURPOSE: To execute the processing when there are plural branched instructions in one instruction and plural branching conditions are established.

CONSTITUTION: This processor is provided with plural processing units 10-1 and 10-2 for executing a prescribed processing, an instruction storage part 20 for storing an instruction 5 composed of plural instruction units 5-1 to 5-n corresponding to the plural processing units 10-1 and 10-2, and a control part 21 for controlling the respective processing units 10-1 and 10-2 by decoding the instruction, and constituted so that the control part 21 extracting the instruction inside the instruction storage part 20 can pass any instruction unit corresponding to the plural processing units 10-1 and 10-2. Further, this device is equipped with a storage part for storing all the established branching destinations when plural branching instructions exist at the instruction unit in one instruction and the plural branching conditions in the plural branching instructions are established.


Inventors:
SAKAMOTO MARIKO
Application Number:
JP5422794A
Publication Date:
October 13, 1995
Filing Date:
March 25, 1994
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F9/38; G06F9/30; (IPC1-7): G06F9/38; G06F9/38
Attorney, Agent or Firm:
Teiichi



 
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