Title:
並列経路周波数分割器回路
Document Type and Number:
Japanese Patent JP2013537736
Kind Code:
A
Abstract:
A parallel path frequency divider (PPFD) includes a low power frequency divider and a high speed latch. A first portion of an oscillating input signal present on an input node of the PPFD is communicated to the divider and a second portion is communicated to the latch. The divider generates a frequency divided enable signal that is communicated to the latch. The latch generates a divided down output signal based on the oscillating input signal and the enable signal. The output signal is insensitive to phase noise present on the enable signal as long as the phase noise on the enable signal is less than one-half of the period of oscillation of the oscillating input signal. Because the noise generated by the low power frequency divider is not propagated to the output signal generated by the PPFD, the PPFD generates low noise, frequency divided signals with relatively low power consumption.
Inventors:
Brown, Garry El.
Cicarini, Alberto
Chao, Dong Jiang
Cicarini, Alberto
Chao, Dong Jiang
Application Number:
JP2013518771A
Publication Date:
October 03, 2013
Filing Date:
July 01, 2011
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
H03K23/00; H03K3/356; H03K23/64; H03K23/66; H04B1/40
Attorney, Agent or Firm:
Kurata Masatoshi
Yoshihiro Fukuhara
Makoto Nakamura
Nobuhisa Nogawa
Toshio Shirane
Takashi Mine
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Morisezo Iseki
Takao Ako
Tadashi Inoue
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Yoshihiro Fukuhara
Makoto Nakamura
Nobuhisa Nogawa
Toshio Shirane
Takashi Mine
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Morisezo Iseki
Takao Ako
Tadashi Inoue
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori