Title:
PARALLEL INTERFACE CIRCUIT FOR DATA
Document Type and Number:
Japanese Patent JP3441275
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To lighten the load on a computer and inform a computer of the head position of data which is transferred by reloading all the data together from a reception clock to a clock having a higher frequency than the reception clock.
SOLUTION: A clock 1 is inputted to a frame synchronizing means 1, a serial/parallel converting means 3, and a clock reloading means 17 and a clock 2 is inputted to a data transfer means 30 and the computer 6. Then the clock reloading means 17 gathers parallel data up to a certain unit and reloads the data from the reception-side clock (clock 1) to the clock (clock 2) having a higher frequency than the reception-side clock, so the data which is inputted continuously can be converted into intermittent data. Further, the intermittent data is transferred to the computer 6 through the data transfer means 30, so if an idle time is generated in a certain amount of data, the computer 6 performs another process by making use of this idle time, so that the load on the computer 6 is lightened.
Inventors:
Yasunori Otsuka
齊藤 ▲隆▼志
Mitsuhiro Yokoya
Hideaki Yokoyama
齊藤 ▲隆▼志
Mitsuhiro Yokoya
Hideaki Yokoyama
Application Number:
JP31236395A
Publication Date:
August 25, 2003
Filing Date:
November 30, 1995
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F5/00; H03M9/00; H04J3/06; (IPC1-7): G06F5/00; H03M9/00; H04J3/06
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Attorney, Agent or Firm:
Fujishima Ijima (1 outside)