PURPOSE: To unnecessitate an external clock circuit by providing a circuit to turn a state memory in a final step to a no-data state when the data stored in the data memory in the final step is read out by an external control signal.

CONSTITUTION: A line 181 is a control line for inputting the data, and a line 184 is control line for outputting the data. A line 182 is a control line to output the possibility of writing an N number of data by showing the presence/absence of the data in the N number of data memories of a data memory 11N from a data memory 111 in the first step, and a line 185 is a control line to output the possibility of reading out the data by showing the presence/absence of the data in a data memory 11M in the final step. In this case, since the output as the inverse of Q from a state storage circuit 13N instantaneously outputs a 0 level when transferring the data, the AND with the inverse of the Q from a state memory 13N-1 in the preceding step is outputted, and the 0 level is outputted without fail only when there is no data at all from the first step to the N-th step.