Title:
PARALLEL PICTURE PROCESSING PROCESSOR
Document Type and Number:
Japanese Patent JPS58181171
Kind Code:
A
Abstract:
PURPOSE:To use one set of picture input and output ports to facilitate making a parallel picture processing processor into an LSI, by performing the local parallel picture processng by the parallel processor having an architecture where plural row-unit processor elements are provided and plural columns of basic modules operated in row units are provided. CONSTITUTION:Picture processing processor basic modules 10A-10C having (#1-#4) each of which has plural processor elements are combined to constitute a parallel picture processing processor 2-I. Each of modules 10A-10C is provided with a picture data input port 24, an input picture shift register 11, an element 12, a partial sum operating circuit 13, and a partial sum accumulating operation circuit 14 for the addition between the operation result of the circuit 13 and data of an operation result data input port 30. One set of the picture data input port 24 and an operation result data output port 35 is used as terminals of each of modules 10A-10C to facilitate making the parallel picture processing processor 2-I into an SLI.
Inventors:
KOBAYASHI YOSHIKI
FUKUSHIMA TADASHI
OKUYAMA YOSHIYUKI
FUKUSHIMA TADASHI
OKUYAMA YOSHIYUKI
Application Number:
JP6232682A
Publication Date:
October 22, 1983
Filing Date:
April 16, 1982
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G06T5/20; G06T1/20; (IPC1-7): G06F15/20
Attorney, Agent or Firm:
Katsuo Ogawa