Title:
PARALLEL PROCESSING AND COMMUNICATION METHOD THEREFOR
Document Type and Number:
Japanese Patent JP3445335
Kind Code:
B2
Abstract:
PURPOSE: To suppress the increase of load of a specific processor by designating a processor and giving the transmission authorization to it when each processor is set in a receivable state.
CONSTITUTION: When a marked processor 10i is set in a receivable state after reception of the information showing the end of transfer of data, an area is secured in a data storing part 13i of the processor 10i for storage of the received data. Then a transmission authorization issuing part 15i of the processor 10i designates an optional processor in the even frequency among all processors. The part 15i issues the information to give the transmission authorization to the designated processor 10j. Meanwhile a transmission authorization detecting/ deciding part 14j which received the transmission authorization giving information transfers the data in quantity that can be received by the processor 10i to this processor that issued the transmission authorization giving information via a communication part 11j and a communication channel 100. When this transfer of data is completed, the transfer end information is sent to the processor 10i.
Inventors:
Yoshifumi Ojo
Application Number:
JP30309293A
Publication Date:
September 08, 2003
Filing Date:
December 02, 1993
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F15/173; G06F13/00; G06F15/16; G06F15/177; H04L29/00; (IPC1-7): G06F13/00; G06F15/177; H04L29/00
Domestic Patent References:
| JP4238566A | ||||
| JP62169259A |
Attorney, Agent or Firm:
Hiroshi Dobashi