PURPOSE: To omit the frame synchronizing circuits and the parallel signal rearraying circuits in number accordant with the array state of parallel signals and to extremely reduce the circuit scale by applying the feedback control to the S/P conversion timing based on the result of frame synchronization.

CONSTITUTION: The parallel signals 2 are inputted to a frame synchronization detecting circuit 13, and an intra-device frame counter 14 outputs an intra-device frame pulse 4. The reception signal inputted to the circuit 13 is compared with the pulse 4 on a time base. Then the coincidence/discordance of timing is detected and an S/P conversion control signal 5 is outputted. When no coincidence of timing is detected, the feedback control is applied to an S/P conversion timing generating circuit 12 with the signal 5. Then an S/P conversion timing signal 3 has a bit shift. Thus the array of the signals 2 is outputted with shift of one bit with the signal 3 that had a l-bit shift. As a result, both the frame synchronizing circuits end the parallel signal rearraying circuits can be omitted in number accordant with the array state of signals 2. Thus the circuit scale is reduced.