PURPOSE: To provide the parallel processor system which is fast in processing speed and simple in hardware constitution.

CONSTITUTION: An AND circuit 6 ANDs transmission end signals from transmitting processor 10-17. Then AND circuits 7, 8 and 9 are installed corresponding to repeating switches 30-33, 40-43, and 50-53 on respective states and AND empty state indication signals from data buffers 10 of the repeating switches 30-33, 40-43, and 50-53 on the respective stages with arithmetic results from the AND circuit 6 or AND circuits 7 and 8 on the preceding stages. Then the arithmetic result of the AND circuit 9 as the final stage from among the AND circuits 7, 8 and 9 is supplied as a reception end signal to respective receiving processors 20-27.