PURPOSE: To more accelerate communication by executing the combination of a read instruction and/or write instruction to a second processor element in one cycle by a first processor element.

CONSTITUTION: First of all, an address AD1 is supplied from a PE1 to a decoder 12. A chip select signal and the write instruction are supplied from the decoder 12 to FIFO memories 6-9. Next, a data for broadcasting is fetched from the PE1 through a data bus 10 to the FIFO memories 6-9. Then, the data is loaded from the respectively corresponding FIFO memories 6-9 to local memories not shown in the figure in PE2-5. Thus, the PE1 enables broadcasting in one write cycle, and the communication such as repeating and broadcasting the data between the processor elements can be more accelerated.