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Title:
PARALLEL PROCESSOR
Document Type and Number:
Japanese Patent JPH0683787
Kind Code:
A
Abstract:

PURPOSE: To make it possible to compute image data arrayed in the vertical direction by successively turning on switches at an interval of two switches by means of a switch control circuit in a shift register and arranging the positions of memories respectively storing vertical image data close to each other.

CONSTITUTION: Flip flops(FFs) 221 to 22M/2 and 241 to 24M/2 are provided to constitute a switch control circuit and signals from respective FFs are extracted through selectors 251 to 25M. When a signal is inputted from a switch ON signal input terminal 21, a switch control signal for turning on a 1st switch 21 is outputted from the FF 221 first because the FFs 221 to 22M/2 are cascade- connected, and then a switch control signal for turning on a 3rd switch 23 is outputted from the FF 222. Finally a switch control signal for turning on the (M-1)th switch 2M-1 is outputted from the FFM/2.


Inventors:
OKI MITSUHARU
Application Number:
JP23724192A
Publication Date:
March 25, 1994
Filing Date:
September 04, 1992
Export Citation:
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Assignee:
SONY CORP
International Classes:
G06F15/80; G06F15/16; G06T1/20; H03M9/00; H04N5/14; (IPC1-7): G06F15/16; G06F15/66; G06F15/80; H03M9/00; H04N5/14
Attorney, Agent or Firm:
Hidekuma Matsukuma



 
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