PURPOSE: To deal with a system having any format by permitting a bit counter length register to designate a bit length to be P/S(parallel serial) converted, comparing it with the value of a counter and generating the timing of the set of parallel data when they coincide.

CONSTITUTION: First, the bit counter length register 11 designates the number of bits to be P/S converted. When the counter 12 is counted up by a clock, the timing of counter load (namely, initialization of counter) snd a timing for setting parallel data are generated from a comparator 13 when the bit counter length register 11 and the value of the counter 12 become equal. In such an example, two flip flops(F/F) are used and the timing is controlled. Parallel data is set in a shift register 14 at the timing when a parallel set is generated, and data is outputted by the clock as serial data.