Title:
パラレル-シリアル変換器及びパラレルデータ出力器
Document Type and Number:
Japanese Patent JP4992947
Kind Code:
B2
Abstract:
A parallel data output device includes a first latch circuit that latches and outputs one of at least two data signals input in parallel in accordance with a first clock signal; a second latch circuit that latches and outputs another of the at least two data signals in accordance with a second clock signal; and a phase set circuit that shifts at least one of a phase of the first clock signal and a phase of the second clock signal based on the phase of the first clock signal and the phase of the second clock signal.
Inventors:
Corner Yukito Ta
Application Number:
JP2009217542A
Publication Date:
August 08, 2012
Filing Date:
September 18, 2009
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03M9/00; H03K5/153
Domestic Patent References:
| JP2004236084A | ||||
| JP4263534A | ||||
| JP2002026726A | ||||
| JP2005079835A | ||||
| JP6244739A |
Other References:
Solid-State Circuits Conference-Digest of Technical Papers,2009.ISSCC 2009.IEEE International,A single-40Gb/s dual-20Gb/s serializaer IC with SFI-5.2 interface in 65nm CMOS,Kouichi Kanda,et al. ,2009年 2月,pp.360-361,361a
Attorney, Agent or Firm:
Tomijio Sasashima